1. Field
The present art relates to a design method and recording medium, and more particularly relates to a method of designing a power supply which is suitable for analyzing power-supply noise occurring in circuit boards such as printed circuit boards (PCB), multichip modules (MCM), or LSI packages or a ground layer analysis model, and a recording medium which is readable by a computer. The present art relates to a design apparatus and CAD system for generating the power source or ground layer analysis model according to such a design method.
2. Description of the Related Art
An analysis model may be created from the circuit board design data using a CAD system. The analysis model may be used to run a circuit simulation. A designer can use the above-mentioned circuit simulation to analyze electrical characteristics of the power source, the ground layer, or the circuit operation of the circuit board.
One such circuit simulator is SPICE (Simulation Program with Integrated Circuit Emphasis). FIG. 1 shows a procedure for generating a conventional power supply mesh model. FIG. 2 is a perspective view of the data generated by the power supply mesh model generation procedure, patterns, and a model. The related art procedure obtains the CAD data of the circuit board, which is subject to the design shown in FIG. 2A, in operation S1. Data for the power supply plane 4 (hereinafter this will simply be referred to as “power supply plane data”), like that shown in FIG. 2B, is created in operation S2. In FIG. 2A, 1 is a surface pattern, 2 is a line pattern, and 3 is a component pin pad. The power supply plane in the CAD data is composed of multiple polygons or line data, but the power supply plane is defined herein as a shape resulting from the synthesis of an interconnect to a power supply conductor in each layer. Power supply planes are also referred to as ground planes.
A power supply pair is extracted in operation S3. One power supply pair is defined herein as the portion in which two power supply planes existing in different layers oppose each other with an insulator between them. A node 6, which is connected by a node link 5 like that shown in FIG. 2C, is generated in operation S4. The shape of a power supply plane 4 is split into a mesh 7 as shown by the hatching in FIG. 2C in operation S5.
The parameters for each inductance, each capacitance, and each resistance are calculated in operation S6. The above-mentioned parameters are corrected in operation S7. Parameter correction is described hereinafter. Each mesh 7 is converted into an equivalent circuit such as an inductance, capacitance, or resistance in operation S8. A power supply mesh model, i.e. analysis model, like that shown in FIG. 2D is then generated. In FIG. 2D, L represents inductances, C represents capacitances, and R represents resistances.
Japanese Laid-open Patent Publication 2003-141205 and Japanese Laid-open Patent Publication 2004-334654 disclosed calculations for the inductance L inductance value and capacitance C capacitance value parameters for the analysis model based on the above-mentioned power supply pair.
Japanese Laid-open Patent Publication 2004-234618 and Japanese Laid-open Patent Publication 2006-31510 disclosed a method of analyzing power supply noise and a method of analyzing jitter caused by power supply noise.
The power supply or ground plane of the circuit board has many holes such as VIA clearance holes. Many miniature power supply pairs are formed from opposing power supply planes through these holes. Many miniature power supply pairs such as these are particularly formed in multilayer boards with two or more power supply layers. Miniature power supply pairs such as these account for a majority of all power supply pairs. The analysis model parameters are calculated based on the power supply pairs, so processing time increases when there are many power supply pairs.
FIG. 3 shows miniature power supply pairs. Identical symbols were provided to identical portions in FIG. 2 and FIG. 3. FIG. 3A shows power supply planes in the VIA periphery. FIG. 3B shows a cross section of power supply planes.
In FIG. 3, 4G-1 through 4G-3 indicate power supply planes (ground planes). 4P-1 and 4P-2 indicate power supply planes. 8 indicates a VIA clearance holes. 9 indicates VIA, GND indicates the ground electric potential. 3.3 V and 2.5 V indicate the power supply voltage. In FIG. 3B, 11-1 through 11-7 indicate power supply pairs. 12-1 and 12-2 indicate miniature power supply pairs. The miniature power supply pair 12-1 is formed from opposing ground planes 4G-1 and 4G-2 through the VIA clearance hole 8. The miniature power supply pair 12-2 is formed from opposing ground planes 4G-2 and 4G-3 through the VIA clearance hole 8.
The parameters of the analysis model can be calculated using the parallel flat plane Expression (1) and Expression (2) like those shown below. However, these Expressions (1) and (2) do not take into account the effect of the edge portion of the power supply planes. Therefore, the above-mentioned calculated parameters are greater than the actual value, so the precision of the analysis results will worsen.
Expression (1) calculates the inductance value L of inductance L between nodes. μO indicates the permeability, d indicates the distance between the layers comprising the power supply pair, and W indicates the width along the node link between the nodes in the power supply mesh. Also, expression (2) calculates the capacitance value C for capacitance C which is located between the nodes. εO indicates the vacuous dielectric constant (8.854×10−12 F/m), εr indicates the relative dielectric constant of the insulators located between the components of the power supply pair, S indicates the area of the mesh created by splitting the power supply pair, and d indicates the distance between the layers comprising the power supply pair.L=μO×d/W  Expression (1)C=εO×εr×S/d  Expression (2)
Corrections made to the parameters from the layer position of the power supply plane near the power supply pair improve the precision of above-mentioned analysis results when the parameters for an analysis model are calculated.
FIG. 4 is a cross-sectional view showing the effect of the edge portion of the power supply planes. Identical symbols were provided to identical portions in FIG. 3 and FIG. 4. in FIG. 4, the arrows indicate the effect on the parameters for the edge portion of the power supply planes. FIG. 4A shows the power supply planes on the periphery of the VIA when the parameters are not corrected. FIG. 4B shows the power supply planes when the parameters are corrected. FIG. 4A takes into account the effect of the ground planes 4G-1 and 4G-2 which form the miniature power supply pair 12-1. However, FIG. 4A does not take into account the effect of the edge portion 15 of the power supply plane 4P-1 which marks off the VIA clearance hole 8. FIG. 4B shows a correction which takes into account the effect of the ground planes 4G-1 and 4G-2 which form the miniature power supply pair 12-1 and the effect of the edge portion 15 of the power supply plane 4P-1 which marks off the VIA clearance hole 8.
FIG. 5 shows a parameter correction process which is performed by operation S7 shown in FIG. 1. A node link 5 is obtained between the nodes 6 to be corrected in operation S71. The next layer for searching after a certain layer in the node 5 to be corrected is targeted in operation S72. The power supply plane 4 is searched within a constant distance from the node link 6 between the nodes 5 to be corrected in operation S73. Whether or not the power supply plane 4 was found within a constant distance from the node link 6 between the nodes 5 to be corrected is judged in operation S74. If the judgment result is NO, then whether or not there is a subsequent layer is determined in operation S75. If the judgment result of operation S75 is YES, then the process proceeds to operation S76. If the judgment result is NO, then this process ends. The next layer for searching is targeted in operation S76. The process returns to operation S73. On the other hand, if the judgment result of operation S74 is YES, the parameters are recalculated based on the distance between a certain layer in the node 5 to be corrected and a certain layer in the power supply plane 4 that was found in operation S77, and then the process ends.
A parameter correction process such as this improves the analysis precision. However, the processing time increases as the number of power supply planes or power supply pairs increases.
Previously, when designing a power supply suited for analyzing power supply noise generated in a circuit board or a ground layer analysis model, there was a problem in which the degree to which the analysis precision could be improved was limited unless the parameter correction process was performed and the processing time increased even though the parameter correction process was performed and the analysis precision was improved.